1. Field of the invention
This invention relates to a method for programming N-channel semiconductor Non-Volatile Memory (NVM). In particular, the programming method of the invention obtains ultra-low programming current down below the sub-microampere range per cell with a very low drain voltage bias. Meanwhile, thanks to no applied source-to-drain electrical field from a floating source electrode, the major obstacle for programming nanometer scale gate lengths of N-channel NVM cell devices in NOR-type NVM cell array associated with the source-to-drain punch-through voltage reduction is then avoided.
2. Description of the Related Art
An N-channel Metal Oxide Semiconductor Field Effect Transistor (MOSFET) is constructed with two N-type source/drain electrodes separated by a P-type channel region with a gate electrode over a dielectric layer on top of the channel region. When the gate of the N-channel MOSFET is applied with a positive voltage relative to the source electrode higher than device's threshold voltage, an inverted electron layer can be formed on the MOSEFET channel surface to electrically conduct the N-type source and drain electrodes. The N-channel semiconductor NVM device is constructed by disposing a layer of charge storage material in between the control gate and the channel region of an N-type MOSFET. The charge storage material can be a conducting material such as a highly doped poly-silicon or a metal conductor, charge trapping dielectric such as a nitride film, or a layer of embedded nanocrystals. By placing electrons in the storage material in an N-channel semiconductor NVM, the threshold voltage of the NVM MOSFET device is shifted to a higher threshold voltage. The states of the threshold voltages of the semiconductor NVM devices can be assigned to represent digital information. For example, digital “1” and “0” can be represented by the low threshold voltage state and high voltage state of the semiconductor NVM devices respectively, or vice versa. Since the semiconductor NVM devices are designed to store electrons in the charge storage material for at least ten years without chip power, the digital data stored in the semiconductor NVM are thus non-volatile.
Placing electrons in the charge storage material for semiconductor NVM devices is called “programming” or “writing”. The most common programming methods for N-channel semiconductor NVM cell devices are Channel Hot Electron Injection (CHEI) for the NOR-type cell array 110 and Fowler-Nordheim (FN) tunneling for the NAND-type cell array 120 as depicted in FIG. 1a and FIG. 1b, respectively. For the NOR-type cell array 110, the CHEI programming voltage biases are directly applied to the source electrode 11, drain electrode 12, control gate 13, and substrate electrode 14 of the N-channel NVM device to generate electrical fields in both gate direction and drain direction for hot electron injection, while for the NAND-type cell array 120, FN programming voltage biases are applied only to the control gate 13 and substrate electrode 14 to establish the sole electrical field toward the gate direction for tunneling electron injection. The two different programming schemes have resulted in that the NVM gate lengths in NAND-type cell arrays are scaled down below twenty nanometers while the NVM gate lengths in NOR-type cell arrays have come to a halt at sub-micrometers. As the semiconductor NVM cell devices are scaled down for smaller geometries with advanced process technology nodes the gate lengths of NVM devices are necessary to shrink accordingly. For shrinking NVM gate lengths to meet the process technology capability, the punch-through voltages, defined as the maximum applicable source-drain voltage difference at the onset of large source-drain leakage current under the MOSFET “off” condition, are also decreased. According to Semiconductor Industry Association (SIA) specification for a nanometer gate length MOSFET, the minimum source-drain punch-through voltage is 1.8V, which is far less than the non-scalable applied source-drain voltage difference of about 3.5 V to about 5 V required for CHEI programming to the N-channel semiconductor NVM. The decreasing punch-through voltage for short gate length has been becoming the major obstacle for scaling down the nanometer gate lengths in NOR-type NVM cell arrays with advanced process technology nodes.
Band-to-band tunneling has been the major programming method for P-channel NVM devices, where a reverse biased voltage applied to the junction of P-type drain electrode and N-type well electrode facilitates the valence band electrons in P-type drain regions tunneling into the conducting band of the N-type well, and a control gate voltage pulse with a positive amplitude higher than the drain voltage is applied to facilitate the band-to-band tunneling in the gate-overlapped depleted surface drain areas known as the P-channel MOSFET Gate Induced Drain Leakage (GIDL) effect for injecting the energetic electrons into the storing material. On the other hand, the application of band-to-band tunneling has never become the programming method for N-channel NVM devices for the following reasons. First, a positive gate voltage relative to the drain voltage for an N-channel MOSFET does not generate the same GIDL effect in the gate-overlapped surface drain regions as that in P-channel MOSFET. The GIDL effect for an N-channel MOSFET can only occur for applying a negative gate voltage relative to the drain voltage as illustrated in FIG. 2. An applied negative voltage to the control gate 13 would cause the electrons repelled away from the storing material instead in programming the N-channel NVM devices. Second, the junction band-to-band tunneling current in an N-channel NVM device is usually small as the example of the junction current versus reverse biased voltage for a typical N-type source/drain and P-type substrate junction shown in FIG. 3. The dominant band-to-band tunneling junction current is in the sub-microampere range and rather small in comparison with the sub-milliampere range required for the conventional CHEI programming. It is the general belief that applying positive voltages to the control gates with reverse drain voltage biases to facilitate drain-substrate band-to-band for programming N-channel NVM device would be ineffective due to the small junction tunneling currents and lack of correct polarity GIDL effect for attracting electrons. On the contrary, as characteristics of the erased and the programmed devices for the 55 nm gate length NVM devices shown in FIG. 4, we have discovered that the nanometer gate length N-channel NVM device can be programmed by applying a positive control gate voltage pulse with low reverse drain voltage biases to facilitate small junction band-to-band tunneling currents. We have also observed that abruptly increasing impurity concentrations in the retrograded P-type channel region and the channel edges from halo ion implantation in the nanometer gate length MOSFET design is correlated to the programming mechanism. It is plausible that the increasing density of energetic secondary electrons generated by the collision energy transfer from heavy holes accelerated in the high gradient electric field from the abrupt impurity distributions near the P-type channel surface is responsible for the enhancement of electron injection efficiency.